Key Box 36 rev A BOM: 443 parts. Largest groups: the AIN front end (8 channels, ADS7038, three
74HC595: about 129 parts), 131 input / output ESD capacitors, 9 NCV7240B, 4 TIC12400.
TLE75008-ESD (datasheet Rev. 1.10): 8 low-side channels, VDS clamp >= 42 V, 330 mA nominal
(all on, 85 C), overload 1.25-2.3 A for 110-260 us then 0.5-1.3 A, latch off; open load in the
off state (85 uA, 3.3 V threshold); VS 7-18 V specified (28 V max, <= 4.2 mA), VDD 3-5.5 V;
IDLE low = sleep with registers reset; PG-TSDSO-24 with a 2.77 x 6.4 mm exposed pad.
URB2424YMD-10WR3: 24 V / 416 mA, same 25.4 x 25.4 x 11.7 mm body as the 6 W part but a
different pin pattern (1 GND, 2 Vin, 3 +Vo, 5 0V, 6 Ctrl).
AD74412R (Rev. A): AVDD 14-26.4 V, DVCC / IOVDD 3.3 V, internal 2.5 V reference and charge
pump; RTD 0-1 MOhm; loop-powered current input. Table 27 asks per channel for RSENSE 100 R 0.1 %,
2 x 2k, 2 x (10k + 10 nF), 68 nF, SMCJ40CA TVS and BAV99, and per chip for about 15 capacitors.
ADI 1k price 9.59 USD; LCSC 25.9 USD, no stock.
Outputs: 9 x TLE75008-ESD replace the NCV7240B (VS = +10V, VDD = +3V3, IDLE = DO_EN, IN0 / IN1
grounded, chain unchanged at 144 bits); new PG-TSDSO-24 footprint with exposed-pad vias.
ESD capacitors: Yageo CA0612KRX7R9BB103 (4 x 10 nF / 50 V, LCSC C700524) arrays, 3 per
TIC12400 and 2 per TLE75008; the input value drops from 15 nF to 10 nF (no 15 nF array found).
10 V rail: LM317 in DPAK (LM317MDT-TR) instead of LM317L SOT-89 for the added TLE75008 VS
load. A fixed 78M10 is not used: its 35 V input rating is below the 35.1 V clamp maximum.
Loop supply: URB2424YMD-10WR3, new footprint and 3D model; ALOOP3 / ALOOP4 unchanged.
AIN front end on 2 x AD74412R: held for an owner decision (see Risks).
Regenerate schematic and PCB (full flow), fix leftovers, exports, BOM; update spec, design
appendix, README and changelog.
AD74412R with the Table 27 circuit saves only about 12 parts (129 -> about 117) and adds about
13 USD per box; the earlier estimate of about 80 parts did not count the per-channel network.
Benefits are accuracy (16-bit, internal reference), hardware current limit and diagnostics, and
loop-powered 2-wire transmitters. Owner to decide before it is implemented.
Item 3 keeps R8 / R9: no part saving there, only the package change.
10 nF instead of 15 nF at the TIC12400 inputs: ESD test to confirm.
TLE75008 VS falls to about 7 V at the 9 V minimum input (edge of the specified range).
LCSC stock of TLE75008-ESD is low (C540043); buy from distribution.
2026-10-25: owner rejected the AD74412R front end ("不做 按推荐处理"); item 5 dropped, the analog front end stays as in rev A.
2026-10-25: schematic regenerated (ERC 0, BOM 357 parts, every row with manufacturer and MPN). Full flow try 3
left 6 unconnected; hand-fixed on a copy (switch/.tmp/fix/r2322/): DRC 0 unconnected, 0 errors, warnings as
before (silk / text height / library footprint only). README and datasheets updated. The flow later ended at 5
unconnected; the hand-fixed board was installed into key-box/ with exports and the 3D package (DRC 0 / 0).