RESEARCH-008 Define the 46-channel, 200 A-total, 100 A-per-channel platform channel architecture

• status: pending
• priority: P1
• owner: /root
• createdAt: 2026-08-26 17:13

Description

The user has fixed the platform envelope: continuous total input current 200 A, 46 output channels, no single channel above 100 A, 12/24 V, with a 100 A-total variant expected to share the same channel count. Research and document the channel-tier architecture that satisfies this envelope: which switching device class serves each tier at 12 V and 24 V, how 46 channels are controlled from one MCU, which sealed connectors and studs carry each tier, what the loss and thermal budget looks like at 200 A, and how the tiers map onto the CTRL/PWR/BUS structure of the canonical report 08.

Acceptance criteria:

1. A Chinese report proposes at least two candidate 46-channel mixes (per-tier count and rating) whose nameplate sum and diversity ratio are stated, with one recommended.
2. Every tier has a named device class for 12/24 V common hardware and, where an integrated 12 V-only part is cheaper, the 12 V / 24 V variant alternative is stated with its voltage limits from official datasheets (SPOC+2 and PROFET+2 12V: 28 V maximum operating; PROFET+ 24V: 36 V operating, 65 V maximum, 58 V/400 ms load dump; Power PROFET+ 24/48V BTH50015-1LUA: 12–54 V nominal; NXP MC33XS2410: 3–60 V; 2ED2410-EM: 3–58 V; TPS1214-Q1: 3.5–73 V).
3. The control architecture shows the pin budget: SPI daisy-chained multi-channel switches for the small-channel tier, IN/DEN/DSEL plus multiplexed IS for the medium tier, gate-driver interfaces for the 100 A tier, and the resulting MCU I/O count.
4. Connector and terminal selection is tied to per-contact ratings from TE data (DEUTSCH size 20: 7.5 A, size 16: 13 A, size 12: 25 A, size 8: 60 A, size 4: 100 A; AMPSEAL tin 8 A / gold 17 A) and to studs for 100 A channels.
5. A loss/thermal budget at 200 A total and at the worst permitted channel combination is given for a sealed IP67 enclosure, with the enclosure-as-heatsink requirement stated.
6. The report states the product-plan implications (relationship to Core HD's 150 A channel and Core M's 46-channel set) as open decisions, without editing any controlled document.
7. Markdown tables, local links, cited URLs, whitespace and git diff --check pass.

ActiveForm

Defining the 46-channel, 200 A-total platform channel architecture.

Dependencies

• blocked by: PLAN-024 approval (PLAN-023, the report 08 consolidation, was completed and its record pruned on 2026-09-08; see docs/changelog.md)
• blocks: schematic partitioning of the 46-channel power board and connector/enclosure selection

Notes

• 2026-08-26 17:13: Claimed after the user fixed the envelope (200 A total, 46 channels, ≤100 A per channel). Evidence gathered: Infineon SPOC+2 BTS72220-4ESA (4 ch, 2×7 A + 2×4 A, SPI daisy chain, 28 V max), PROFET+ 24V BTT6020/6030 (7 A / 6 A, 36 V operating, 65 V max, pin-compatible with PROFET+ 12V), NXP MC33XS2410 (4 ch, 3–60 V, 1.8 A/ch, SPI daisy chain, 12-bit ADC), Power PROFET+ BTH50015-1LUA (24/48 V, 32–35 A), 2ED2410-EM + TOLL MOSFET pattern for the 100 A tier, TE DEUTSCH/AMPSEAL contact ratings. Core M already has 46 channels (4×15 A + 12×10 A + 30×5 A, 80 A total); the new envelope overlaps Core M's channel count and Core HD's current class.
• 2026-08-26 17:15: User directed the design to reference the Core HD product; plan revised to a Core HD-derived 46-channel mix with SDCR100 / SP4210D as public analogues.