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PLAN-024 Define the 46-channel, 200 A-total, 100 A-per-channel platform channel architecture ​

  • status: draft
  • createdAt: 2026-08-26 17:13
  • approvedAt: (pending)
  • relatedTask: RESEARCH-008

Context ​

  • User-fixed envelope (2026-08-26): total continuous input 200 A, 46 output channels, maximum 100 A on any channel, 12/24 V. A 100 A-total variant is assumed to keep the same 46 channels (assumption to confirm).
  • Canonical report bizplan/research/08-open-source-high-current-pdm-pcb-reference.md (session hardware-d2, PLAN-022) already fixes the platform principles: 100 A / 200 A are total currents, CTRL/PWR/BUS three-tier structure, copper busbar for the 200 A trunk, Hall main-current sensing, LP/MP/HP channel classes, external contactor or separately validated MOSFET module for high-current outputs. PLAN-023 (draft, same session) proposes to rewrite report 08 and delete the parallel draft 08-open-source-pdm-and-high-current-switch-reference.md.
  • bizplan/PRODUCT-PLAN.md currently splits the same envelope across two SKUs: Core M (46 ch: 4×15 A + 12×10 A + 30×5 A, 80 A total) and Core HD (1×150 A + 1×100 A + 2×40 A + 6×30 A + 8×20 A, 200 A total). The new envelope merges Core M's channel count with Core HD's current class and drops the 150 A channel.
  • Device evidence (official pages/datasheets, 2026-08-26):
    1. 12 V-class integrated switches are limited to 28 V maximum operating voltage: SPOC+2 BTS72220-4ESA (4 ch, 2×7 A + 2×4 A, 5.5/13.5 mΩ, SPI daisy chain, 3.3/5 V logic), PROFET+2 12V (BTS7002-1EPP 21 A class used by dingoPDM). Usable only in a 12 V-specific variant.
    2. 24 V-capable integrated switches: PROFET+ 24V BTT6020-1ERA (20 mΩ, 7 A, 5–36 V operating, 65 V max, 58 V/400 ms load dump, pin/function compatible with PROFET+ 12V), BTT6030-2ERA (2 ch, 6 A/4 A); PROFET+ 24V family up to 4 channels and 10 A; Power PROFET+ BTH50015-1LUA (12–54 V nominal, 6–60 V extended, 32–35 A, no official paralleling guidance per PLAN-023); NXP MC33XS2410 (4 ch, 3–60 V, 1.8 A/ch, parallel-pair 3.6 A, SPI daisy chain, 12-bit ADC, ISO 16750-2).
    3. 100 A tier: 2ED2410-EM (3–58 V) driving back-to-back paralleled 80 V TOLL MOSFETs, per Infineon HC-PDU; TI TPS1214-Q1 (3.5–73 V, integrated I²t) as alternative driver.
    4. Sealed connectors: DEUTSCH HDP20 (2–47 cavities, contact sizes 4/8/12/16/20 = 100/60/25/13/7.5 A), DRC (24–80 cavities, sizes 16/20 = 13/7.5 A, PCB mount), AMPSEAL (8 A tin / 17 A gold), AMPSEAL 16 (13 A, IP67/IP6K9K).
    5. Core HD reference (user instruction 2026-08-26 "reference the Core HD product"): Core HD's target spec is 1×150 A + 1×100 A + 2×40 A + 6×30 A + 8×20 A heavy channels plus small-channel spares, 200 A total, 24 V-only automotive base customised to 12/24 V, 2×CAN-FD + RS-485, static ❤️ mA, ~264×184×49 mm (bizplan/PRODUCT-PLAN.md). The base vendor is confidential; the closest public analogues in the Senptec-class inventory (report 06a) are SDCR100 (42 ch: 1×150 A, 1×120 A, 2×40 A, 1×30 A, 8×20 A, 7×10 A, 6×5 A, 12×3 A, 4×1 A; 16–32 V; 220×165×44 mm; 1 CAN; E-Mark R10) and SP4210D (43 ch: 1×150 A, 8×50 A, 34×15 A; 9–32 V; 317×251×48 mm). Core S and Core M map exactly onto KM2210 (22 ch) and KM4658 (46 ch), so the 46-channel count of the new envelope equals Core M's channel count while the current class equals Core HD's.
    6. Benchmarks: MoTeC PDM32 (32 outputs, 120 A total), Ecumaster PMU-16 (16 outputs, 150 A), Core HD nameplate sum ≈ 670 A over a 200 A bus (diversity ≈ 3.3).

Proposal ​

  1. Add bizplan/research/10-46-channel-200a-platform-channel-architecture.md (Chinese, evidence date 2026-08-26), scoped to the channel architecture and PCB partition of the 46-channel platform; it builds on report 08 and does not restate its open-source inventory.
  2. Channel mix, Core HD-derived per the user's instruction (both candidates = 46):
    • Mix A (recommended baseline, Core HD-derived): 2×100 A + 2×40 A + 6×30 A + 8×20 A (the 18 Core HD heavy channels with the 150 A channel capped at 100 A) + 28 small channels sized like SDCR100's lower tiers, e.g. 8×10 A + 8×5 A + 12×3 A. Nameplate ≈ 776 A, diversity ≈ 3.9. The 100 A and 40 A channels (4) need gate-driver + external MOSFET stages at 12/24 V; 30 A channels map to BTH50015-1LUA; 20 A and below to integrated switches.
    • Mix B (cost alternative): 2×100 A + 4×35 A + 8×20 A + 32×≤7 A. Nameplate ≈ 670 A, diversity ≈ 3.35. Only two gate-driver channels, but it departs from Core HD's 40 A / 30 A tiers.
    • The report keeps Core HD's channel taxonomy and stud-terminal heavy channels, uses SDCR100 / SP4210D packaging and tier ratios as public analogues, and states the 100 A-total variant as the same 46 channels on a 100 A BUS assembly (assumption to confirm).
  3. Device strategy per tier, with the 12/24 V decision made explicit:
    • Strategy 1 (single 12/24 V hardware): HP = 2ED2410-EM + 2×2..2×3 IAUT300N08S5N012 per channel; MP = BTH50015-1LUA; LP = TPS1214-Q1 + one 80 V FET per channel (or BTH50015 derated); micro = NXP MC33XS2410 ×8 (60 V) or PROFET+ 24V quad. Fewest SKUs, higher BOM cost, no 28 V-limited parts.
    • Strategy 2 (12 V and 24 V BOM variants on shared footprints): micro/LP tiers use SPOC+2 / PROFET+2 12V on the 12 V build and PROFET+ 24V / MC33XS2410 on the 24 V build, exploiting Infineon's pin/function compatibility between PROFET+ 12V and 24V; HP/MP unchanged. Lower cost on the volume 12 V build, two validated BOMs, hardware variant ID mandatory.
    • Report recommends Strategy 1 for the first prototype and Strategy 2 as the cost-down path once 12 V volume is known. Because the Core HD base is 24 V-only and 12/24 V is already a custom requirement, the report also states which tiers the base vendor must change for 12 V.
  4. Control architecture: eight SPI quad switches in one daisy chain (32 channels, ~5 MCU pins), 12 discrete IN + 4 DEN/DSEL groups + multiplexed IS into ADC for MP/LP, two 2ED2410 interfaces (EN/INA/INB/INT/DG0/DG1/CSO ×2), Hall trunk sensor, NTC per HP stage, variant ID; STM32 with 2×CAN-FD + RS-485 per Core HD spec.
  5. Connector plan: HP on M8 studs (trunk M8/M10); MP on M6 studs or HDP20 size-8 contacts; LP on HDP20 size-12 (25 A) contacts; micro + inputs on DRC 60/64-way PCB-mount (size 16/20) or AMPSEAL 35; state the contact-rating-bound channel currents as dingoPDM does.
  6. Loss and thermal budget: trunk ≤250 µΩ (10 W at 200 A); HP 2×100 A ≈ 16 W hot; MP 4×35 A ≈ 17 W; LP/micro at realistic concurrency; total 40–60 W in a sealed enclosure → enclosure must be the heatsink; give the worst permitted channel combination and the derating curve requirement.
  7. PCB partition per report 08: CTRL board common; PWR board carries all 46 branch switches and the two HP stages; BUS assembly carries the 200 A trunk, Hall sensor, HP taps; 100 A-total variant = same CTRL/PWR, 100 A BUS assembly, HP stages populated for 100 A (assumption).
  8. Product-plan implications listed as open decisions only: whether this platform replaces Core HD + Core M or becomes a new SKU; the dropped 150 A channel; Core M's PWM/half-bridge and analog-input features not covered here.
  9. Verification: table shape, local links, URL reachability, whitespace, git diff --check; complete RESEARCH-008 / PLAN-024 and changelog.

Risks ​

  • Two sessions are editing the same report family; PLAN-023's rewrite/deletion of report 08 files and this plan must be sequenced by the user to avoid conflicting canonical documents.
  • Integrated-switch nominal currents (7 A, 35 A) are datasheet values at 85 °C on JEDEC boards, not sealed-enclosure ratings; the report must not present them as board ratings.
  • Paralleling BTH50015-1LUA is not officially documented (PLAN-023 finding); any 40 A integrated channel is therefore excluded from Mix B.
  • The ≤7 A tier at 24 V relies on NXP MC33XS2410 (1.8 A/ch nominal) or PROFET+ 24V quads; channel currents there are lower than Core M's 5 A nameplate and must be checked against real marine loads.
  • Connector cavity counts (HDP20 max 47, DRC max 80) constrain the physical layout; a 46-output + inputs box may need two DRC-class connectors plus studs, affecting enclosure size beyond Core HD's 264×184 mm.

Scope ​

  • One new Chinese report 10 (target 200–300 lines).
  • RESEARCH-008 / PLAN-024 tracking and changelog updates.
  • No change to PRODUCT-PLAN, BUSINESS-PLAN, SKU ratings, supplier selection or RFQ; no edit to either report 08 file.

Alternatives ​

  1. Fold the 46-channel architecture into the PLAN-023 rewrite of report 08: one document, but couples the user's new envelope to a rewrite/deletion decision owned by another session and makes report 08 much longer.
  2. Amend PRODUCT-PLAN directly with the new envelope: premature before the tier/device strategy is accepted.
  3. Recommended: standalone report 10 now; product-plan change as a later controlled task.

Annotations ​

  • 2026-08-26 17:13: Investigation complete and proposal drafted; awaiting approval. Attempted to notify session hardware-d2 to hold PLAN-023 file deletion until both plans are ruled on; the session was not reachable, so sequencing of PLAN-023 and PLAN-024 is left to the user.
  • 2026-08-26 17:15: User instructed to reference the Core HD product. Plan revised: Mix A (Core HD heavy channels with 150 A capped at 100 A plus 28 small channels) is now the recommended baseline; Senptec SDCR100 / SP4210D added as public analogues; Mix B kept as cost alternative. Awaiting proceed.
  • 2026-08-26 17:26: Report number changed from 09 to 10 on the user's instruction because 09 is reserved by other work in progress.

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