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20261023-1233-key-box-adc-voltage-inputs Key Box 36: dedicated ADC and a 0-10 V mode for the eight analog inputs

  • status: completed
  • createdAt: 2026-10-23 12:33
  • approvedAt: 2026-10-23 12:45
  • relatedTask: 20261023-1233-key-box-adc-voltage-inputs

Context

章节标题：“Context”
  • AIN front end today: 1k 0.1 % pull-up to +5V on the terminal side of a 0.1 A PTC, 100 R shunt to a DMN6140L (U14 74HC595), 100 R + 15 nF to TIC12400 U11 / U12 IN11-IN14 (ADC mode, 0-6 V, 10 bit); U11 / U12 IN15 read +5V.
  • The fixed pull-up loads a 0-10 V sensor (about 5 mA at 0 V and at 10 V) and the TIC ADC saturates at 6 V; a divider in front of the TIC is ruled out by its +-110 uA leakage.
  • GPIO: IO11 is the only spare. U16 QG / QH are spare.
  • ADS7038 (SBAS979C): 8 ch, 12 bit, 1 MSPS, SPI up to 60 MHz; AVDD 2.35-5.5 V is the reference; DVDD 1.65-5.5 V; SDO hi-Z while CS is high; input 0-AVDD; pin current <= 10 mA; gain error +-0.075 % FSR; WQFN-16 3 x 3 mm. No ALERT pin when all 8 channels are analog.

Proposal

章节标题：“Proposal”
  • ADS7038IRTER: AVDD from +5V via 10 R + 1 uF + 100 nF (ratiometric with the pull-ups), DVDD +3V3, DECAP 1 uF; SCLK / SDI / SDO on the shared SPI; CS = IO11 with a 10k pull-up.
  • Per channel:
    • Pull-up switch: back-to-back dual PMOS (BSS84DW, 50 V) between +5V and the 1k pull-up; 100k and a 12 V zener gate-source; 10k to a 2N7002 driven from a third 74HC595 (100k gate pull-down). It blocks both directions, so a 0-10 V or shorted input does not back-feed +5V.
    • Divider from the PTC output: 30.1k / 20k 0.1 % (node full scale about 12.5 V, 3.06 mV / LSB), 10 nF at the ADC pin; replaces the 100 R + 15 nF to the TIC.
    • Shunt path unchanged except the 100 R 0.1 % moves to 2512 for short-circuit pulses.
  • Third 74HC595 after U16 QH': QA-QH = pull-up enable 1-8; /OE = NOT DO_EN, so every channel is high impedance through reset and boot.
  • Modes: Ohm = pull-up on, shunt off; mA = shunt on, pull-up off; voltage = both off.
  • Ranges (12 bit, before averaging): Ohm 0-1000 R (about 0.9 R / LSB at 190 R, 1.2 R at 400 R, 2.4 R at 1 k; covers 240-33 R senders); 4-20 mA about 0.031 mA / LSB, 2.0 V burden at 20 mA; 0-10 V (and 0-5 V) about 3 mV / LSB, 50 k input.
  • Faults: in Ohm mode a reading above 5 V turns the pull-up off; in mA mode firmware polls every <= 1 ms (ADS7038 window flags) and turns the shunt off, the PTC is the backup; voltage mode withstands 32 V (about 0.6 mA into the ADC clamp through 30.1k).
  • TIC12400 U11 / U12 IN11-IN14 become unused; IN15 keeps reading +5V as a drift monitor.
  • PCB: regenerate the board with the full flow (the 2026-10-23 hand routing is lost) and redo hand fixes as needed.
  • Docs: spec §2.1 and KEY-30 (three modes, ranges, high-Z default), design appendix §2.3 (circuit, GPIO, limits, cost), guide V-11 (0 / 5 / 10 V and 240 / 1000 R points), brief, README, changelog.

Risks

章节标题：“Risks”
  • mA and voltage accuracy follow the absolute +5V (LMR36510); after production calibration the drift is about +-0.5 %. A separate reference would also need the pull-ups on it.
  • No hardware over-current interrupt in mA mode: the shunt sees about 9 W until firmware or the PTC cuts it.
  • About 60 more parts in the analog area; the full routing flow takes 5-6 h and left about 7 nets for hand routing last time.
  • All 23 GPIO used.

Scope

章节标题：“Scope”

switch: tools/gen_key_box.py, tools/gen_key_symbols.py (ADS7038, BSS84DW if missing), tools/gen_key_pcb.py, regenerated key-box/ outputs and README. docs: 4 files under bizplan/product/switch/key/, changelog, task / plan.

Alternatives

章节标题：“Alternatives”
  • External 0-10 V to 4-20 mA converter per sensor: no hardware change; not chosen.
  • One pull-up switch per connector (4 channels): about 24 fewer parts, but Ohm and voltage channels cannot share a connector; not chosen.
  • PMOS + Schottky pull-up switch: fewer parts, but the diode drop drifts with temperature and breaks the ratiometric Ohm reading; not chosen.

Annotations

章节标题：“Annotations”
  • 2026-10-23: owner chose option B ("用方案B").
  • 2026-10-23: owner approved ("开始").
  • 2026-10-23: the 4-layer flow left 49 unconnected / clearance items on try 1; owner approved 6 layers ("可以"): F signal, In1 GND, In2 / In3 signal, In4 VPROT, B signal; Freerouting routes on 4 layers and the import moves the inner tracks.
  • 2026-10-23: owner approved power modules ("输出是24v回路 2，按表 3，加gnd网络"): +5V K7805 1 A module, TIC VS K7809 module, loop supply URB2424YMD-6WR3 isolated 24 V / 250 mA (return tied to GND), keep TLV75533 / L78L05 / LM74800; TPS2H160 GND network (1k || diode).
  • 2026-10-23: K7809 needs 13 V in and K7805 needs 8 V in (Mornsun data sheets); owner confirmed ("可以 确认"): +5V K7805T-1000R3 (SMD), input spec 9-32 V, TIC VS stays on LM317L, loop supply URB2424YMD-6WR3, TPS2H160 GND network.
  • 2026-10-23: power-module change implemented in the schematic (ERC 0) and placement; spec / design / guide / README updated; full 6-layer routing flow rerun.
  • 2026-10-24: owner approved the pre-handoff fixes ("可以，开始处理"): U19 and its AVDD / DECAP / DVDD capacitors fixed next to the ADC (C623 had been placed about 25 mm away), URB module holes to the recommended 1.5 mm, 3D models for both Mornsun modules, MPN / manufacturer / LCSC for every BOM line; full routing flow rerun.
  • 2026-10-24: done; board DRC with schematic parity 0 errors / 0 unconnected after one hand-routed fix (U1 pin 12 VFET); BOM complete (manufacturer + MPN on every line).